1. Field of the Invention
The present invention relates to a cache memory control system used in a computer system and particularly relates to a cache memory control system used in a computer system specialized in graphics and image processing.
2. Description of the Related Art
FIG. 9 is a block diagram showing an example of a conventional cache memory control system.
A conventional cache memory control system used in a computer system includes, as shown in FIG. 9, a cache memory 402 to store a portion of a main memory 401 and a cache controller 403 to control the data flow for the cache memory 402. When a host processor 400 issues a data read request to the main memory 401, if that data exists in the cache memory 402 (referred to as "cache hit"), the cache controller 403 rapidly transfers the data from the cache memory 402 to the host processor 400.
If the data requested by the host processor 400 does not exist in the cache memory 402 (referred to as "cache miss"), the cache controller 403 transfers the data from the main memory 401 to the host processor 400. At the same time, the cache controller 403 transfers a continuous block of several bytes of data, including the requested data to the cache memory 402 in order to raise the probability of a cache hit for the next data read request.
For example, suppose the host processor 400 sends a read request for data 502 to the main memory 401, as shown in the FIG. 9. For a cache miss, the cache controller 403 transfers the data 502 hot only from the main memory 401 to the host processor 400 but it also transfers 16 bytes of data, from data 501 to 516 (including to data 502), as a block to the cache memory 402 for storage.
The conventional cache memory control system as described above transfers, upon a cache miss, a continuous bock of several bytes of data, including the data causing the cache miss, from the main memory to the cache memory so as to raise the cache hit ratio.
However, in a computer system for graphics and image processing, a plurality of data adjacently positioned in a display screen are located at discontinuous addresses in the main memory. Therefore, conventional cache control of replacing the data block of continuous addresses, including the one for the requested data, may cause many cache misses when the data adjacent on the display screen are sequentially read out, which may result in a lower processing speed. In other words, a computer system for graphics and image processing cannot take advantage of cache memory, which is provided for rapid data transmission.